A Large Scale Image Processing System TIP-4 Prototype

data flow VLSI processor ImPPs( Image Pipelined Processor :pPD7281). lmPP capable of performing 5 million instructions per second(5 MIPS), so TIP-4 has maximum processing speed of 2560 million instructions per second(2. 5GIPS) The prototype system TIP-4P that has actually been developed has 64 ImPPs, thus the peak computation rate for TIP-4P is 320 MIPS. To use 512 ImPPs efficiently. TIP-4 has the following hardware and software characteristics. (1)Processors are devided into clusters. Each cluster consists of 8 ImPPs, interface LSI MAC and 512K words local memory. ImPPs and MAC are connected in a pipeline token ring bus. (2)The pipeline token ring bus is also there through clusters to support intercluster comunication. (3)There is a large global memory that holds a large image and can exchange data with a local memory through a very fast block transfer data bus. (4)To process a set of programs efficiently. a data flow process scheduling monitor was developed that controls processes and resourcess cheduling. A catalog language has also been developed to define parallel and serial process accomplishment. l N T R O D U C T l O N NEC has been developing a static data flow machine especially for image processing since 1982" A static data flow VLSI processor. ImPP. was made in 1984. Figure 1 shows an lmPP blockdiagram. An lmPP is a VLSI processor. which has a flexible pipeline architecture and data flow architecture. The data flow architecture makes it easy to set up the multiprocessor configration. ImPPs are designed to be connected sequentially in an array. Figure 2 shows a TIP-3 system blockdiagram. as an example of an lmPP multiprocessor system. TIP-3 consists of 8 ImPPs. MAGIC(Memory Access and General Bus Interface Chip). memory and host computer. MAGIC is a peripheral LSI that supports memory access. host computer access and program load. TIP-3 has a 40 MIPS maximum processing speed. However. the processing power is not enough to process larger images or video images. So.the authers decided to make TIP-4. which uses TIP-3 as a cluster. and multiple clusters work together. This paper first describes the TIP-4 hardware architecture that enables 512 ImPPs to work together. Second, software environment is shown. Then performance evaluation for a prototype system is presented. S Y S T E M A R C H I T E C T U R E Figure 3 shows a TIP-4 cluster. The cluster IPU (Image Processing Unit) consists of 8 ImPPs. interface LSI MAC(Memory Access Controller), local memory and a few interface busses. Figure 4 shows the basic TIP-4 configuration. Clusters are conected with the main bus, image bus and inter-cluster pipeline ring bus. i Figure 1. ImPP Architecture lAPR Workshop on CV Special Hardware and Industrial Applications OCT.12-14, 1988, Tokyo Figure 2. I wage Processing I N B U S I N T E R C L U S T E R I M A G E B U S P I P E L I N E R I N G B U S Figure Processing